1. Field of the Disclosure
Generally, the present disclosure relates to semiconductor devices and manufacturing techniques in which transistor elements may be formed on the basis of a very thin crystalline semiconductor material.
2. Description of the Related Art
Significant progress has been made in the field of semiconductor devices, mainly driven by a steady reduction of the critical dimensions of circuit elements in such semiconductor devices. In sophisticated semiconductor devices, a major part of the circuit elements provided therein are typically based on CMOS technology, which, in turn, is based on respective field effect transistors having a channel region whose conductivity is controlled by an appropriate control voltage. The control voltage is typically applied by using an appropriate electrode structure, typically referred to as a gate electrode structure, which includes an electrode material that is separated from the semiconductor material of the channel region by a dielectric material. Consequently, upon operating such a field effect transistor, the current flow in the channel region from the source region to the drain region may be efficiently controlled by applying the control voltage to the gate electrode structure, wherein transistor characteristics, such as threshold voltage, current drive capability and the like, may depend on various device parameters.
Generally, the continuous reduction of critical dimensions of field effect transistors, in particular, the length of the channel region, may contribute to increased overall packing density, while a certain degree of performance gain may also accompany a size reduction of the transistors. On the other hand, the ongoing reduction of critical dimensions of field effect transistors is also associated with significant problems that have to be addressed in order to not unduly offset the performance advantages that would be generally achieved by reducing the critical feature sizes. For example, effective controllability of the channel region of the transistor elements strongly depends on the capacitive coupling of the gate electrode structure to the channel region and becomes typically more complex upon reducing the channel length of the transistors. Therefore, a thickness of the gate dielectric material must be appropriately adapted so as to provide sufficient capacitive coupling, while still ensuring appropriate dielectric strength with respect to the supply voltage and/or control voltage applied upon operating the transistor element, if these voltages are different from each other. Therefore, in complex semiconductor devices, different types of gate electrode structures, including different types and/or materials with different thicknesses, may be typically used so as to comply with the overall device requirements, since, typically, transistor elements in a complex integrated circuit may be designed for different purposes. For example, in certain logic paths of a more or less complex controller circuit, increased switching speed of the respective field effect transistor may be of high priority, thereby requiring extremely reduced gate length dimensions in combination with respectively adapted gate electrode structures. In order to not unduly increase overall power losses, for instance, by static and dynamic leakage currents, attempts have been made to design the respective transistors so as to enable operation at moderately low supply voltages, such as approximately 1 V or even less in sophisticated currently available semiconductor devices.
In other device areas, an increased operating voltage may be generally required, for instance, for providing appropriate matching to signal processing based on external signals and/or signals provided by different device portions, which may generally operate on the basis of an increased supply voltage. For example, input/output portions of a complex integrated circuit may frequently operate at elevated supply voltages compared to an “internal” reduced supply voltage for sophisticated digital circuit areas, wherein 2.5 to 3.3 V are frequently used operating voltages. Consequently, due to these significant increased supply voltages and, thus, gate voltages, a corresponding adaptation of certain transistor parameters, such as thickness of the gate dielectric material and the like, may have to be taken into consideration.
Upon the further reduction of critical dimensions aimed at enhancing overall performance and, in particular, for providing superior packing density of such integrated circuits, different approaches have been developed, for instance, in terms of enhancing overall channel controllability. One promising approach involves the provision of substantially fully depleted channel regions with reduced dopant concentration. To this end, a very thin basic semiconductor material, such as crystalline silicon material, crystalline silicon/germanium material and the like, may be provided with very low dopant concentration or even as an intrinsic material, thereby contributing to the reduction of scattering events and any scattering centers, which are typically associated with the incorporation of a dopant species. Furthermore, a substantially full depletion of the channel region may be achieved for a certain transistor state when a substantially non-conductive channel is required. In such sophisticated planar transistor configurations, the very thin basic semiconductor material, which may have an initial thickness of 15 nm and significantly less, may be combined with an appropriately designed gate electrode structure, thereby obtaining transistor elements having a channel length of approximately 30 nm and less. Furthermore, since the very reduced thickness of the semiconductor material may impart certain constraints with respect to providing highly conductive drain and source regions, such regions may be typically formed on the basis of a raised drain and source architecture in which an appropriately highly in situ doped semiconductor material may be grown on top of the initial semiconductor material.
Although this basic device configuration of transistors in sophisticated semiconductor devices may be highly effective for transistor elements designed for critical signal paths, it turns out, however, that, upon the further reduction of overall dimensions, significant reliability issues may arise for transistor elements having the same basic configuration in which an increased supply voltage has to be applied in order to comply with overall functional constraints of certain circuit portions, such as I/O (input/output) portions and the like. It has been recognized that corresponding reliability issues, i.e., degradation of device performance and/or premature failure of semiconductor devices, may be associated with hot carrier injection (HCI), which is a phenomenon occurring at increased supply voltages, wherein charge carriers injected at the source region may gain sufficient energy so as to overcome the potential of the gate dielectric material. That is, typically at the drain side, a certain amount of charge carriers may enter into and possibly penetrate through the gate dielectric material, thereby increasingly changing overall transistor characteristics, such as threshold voltage, leakage current behavior and the like.
In view of the situation described above, the present disclosure relates to techniques and semiconductor devices in which transistor elements may be formed on the basis of a thin basic semiconductor layer, while avoiding or at least reducing the effects of one or more of the problems identified above.